The testing of integrated circuits and of their interconnections in packaging is an important task in the manufacturing of electronic and data processing equipment. It is particularly important that the testing methods are fast and do not require much preparatory operations for their execution.
In principle, testing can be done by applying power and data signals to, and extracting resulting data signals and electrical conditions from, circuitry through the regular connection pins, or through mechanical contact probes. Such testing is, however, slow and not very effective because of the limited number of connections which can be made. It is, therefore, not well suited for highly integrated circuits and dense packaging which are used today.
Therefore, some methods of contactless testing have been recently suggested using either electron beam or laser technology. E-beam testing was described in an article by E. Menzel et al.: "Fundamentals of Electron Beam Testing of Integrated Circuits", published in Scanning, Vol. 5 (1983), pp. 103-122. The E-beam is used as a contactless probe, either in a passive or active mode. However, the utilization of electron beams for testing has certain disadvantages and limitations. These are the need for vacuum environment during testing and the fact that individual pads have to be tested sequentially, i.e. no full-package approach (flooding the substrate with a wide beam) is possible. During such a process the insulating substrate would charge up and eliminate contrast against the pads.
More recently, the use of a laser beam for integrated circuit testing has been suggested. The photons of a laser beam can excite electron emission from the target, and the laser beam can thus be used for contactless testing of electronic circuitry.
European Patent Application publication No. 0,196,475 (U.S. counterpart Pat. No. 4,644,264 entitled "Noncontact Testing of Integrated Circuits" discloses a technique of covering an integrated circuit chip by an insulating layer and a metallic overlayer, and the directing a laser beam to a test point on the chip causing tunneling of electrons in an intensity which depends on the potential of the respective point. The respective pulse generated in the metallic overlayer is then evaluated.
In European Patent Application No. 0,216,077 (U.S. counterpart Ser. No. 778,823 filed Sept. 23, 1985 now U.S. Pat. No. 4,703,260) a testing procedure is described in which laser light is directed to the entire surface of a circuit chip, and in which that laser light causes generation of photoelectrons in dependance of the voltage present at each point. The electrons generated are directed either to a luminescent target whose image is then evaluated, or the electrons are directed to channel plates and further to a luminescent target and an optical processing system. Also shown is the utilization of a passivation layer, a luminescent layer, and a metallic overlayer on a circuit chip to attain, with the aid of laser light directed to the whole chip area, voltage dependent photon-assisted electron tunneling through the passivation layer and to thus allow testing in air.
In both systems disclosed in the two above-mentioned European patent applications, power and test data signals have to be applied to the tested circuits through normal pins and chip connections, to bring them into an operating status that is to be detected in the testing procedure. This is a limitation of the testing possibilities.